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【压缩文件】 [ FreeCourseWeb.com ] Udemy - Introduction to VHDL- Understand VHDL and how it is used to describe digital circuits.zip
收录时间:2020-03-25 文档个数:1 文档大小:614.2 MB 最近下载:2024-11-14 人气:2369 磁力链接
  • zip[ FreeCourseWeb.com ] Udemy - Introduction to VHDL- Understand VHDL and how it is used to describe digital circuits.zip 614.2 MB
【文档书籍】 Digital Electronics - A Practical Approach With VHDL 9th Edition.pdf
收录时间:2020-01-24 文档个数:1 文档大小:33.6 MB 最近下载:2024-11-12 人气:4640 磁力链接
  • pdfDigital Electronics - A Practical Approach With VHDL 9th Edition.pdf 33.6 MB
【文档书籍】 Embedded SoPC Design with Nios II Processor and VHDL Examples.pdf
收录时间:2020-01-30 文档个数:1 文档大小:32.6 MB 最近下载:2024-11-09 人气:1182 磁力链接
  • pdfEmbedded SoPC Design with Nios II Processor and VHDL Examples.pdf 32.6 MB
【文档书籍】 Circuit Design - Know It All (Newnes, 2008).pdf Circuit Design with VHDL - V.Pedroni (2004) WW.pdf
收录时间:2020-02-01 文档个数:5 文档大小:32.4 MB 最近下载:2024-11-12 人气:206 磁力链接
  • pdfCircuit Design - Know It All (Newnes, 2008).pdf 27.1 MB
  • pdfCircuit Design with VHDL - V.Pedroni (2004) WW.pdf 5.2 MB
  • txtMore Books.txt 2.9 kB
  • urlImportant. Read me .url 238 Bytes
  • txtTorrent downloaded from Demonoid.com.txt 49 Bytes
【文档书籍】 HDL Books - VHDL FPGA CPLD Verilog Digital Electronics eBook
收录时间:2020-02-03 文档个数:60 文档大小:1.2 GB 最近下载:2024-11-13 人气:5894 磁力链接
  • pdf0131972553 - (2005) Digital Fundamentals.pdf 492.0 MB
  • pdf0126912955 - (2000) Engineering Digital Design.pdf 50.6 MB
  • pdf0792397460 - (1996) LOGIC SYNTHESIS AND VERIFICATION ALGORITHMS.pdf 41.7 MB
  • pdf0965193438 - (1996) HDL Chip Design- A Practical Guide for Designing, Synthesizing and Simulating ASICs and FPGAs Using VHDL or Verilog.pdf 40.6 MB
  • pdf0471720925 - (2006) RTL Hardware Design Using VHDL Coding for Efficiency, Portability, and Scalability.pdf 35.8 MB
  • pdf0072460857 - (2005) Fundamentals of Digital Logic with VHDL Design.pdf 35.6 MB
  • pdf0132543036 - (2011) Digital Electronics - A Practical Approach with VHDL - 9th Edition.pdf 33.6 MB
  • pdf0470828498 - (2011) Design for Embedded Image Processing on FPGAs.pdf 28.7 MB
  • pdf0070471649 - (1999) Verilog Digital System Design.pdf 28.3 MB
  • pdf0134516753 - (1996) Verilog HDL A Guide to Digital Design and Synthesis B.pdf 22.4 MB
  • pdf0470185317 - (2008) FPGA Prototyping by VHDL Examples - Xilinx Spartan-3 Version.pdf 22.3 MB
  • chm0131543180 - (2005) Practical FPGA Programming in C.chm 18.2 MB
  • pdf1402055293 - (2007) Processor Design System-On-Chip Computing for ASICs and FPGAs.pdf 15.6 MB
  • pdf0387284850 - (2006) FPGA Implementations of neural networks.pdf 14.7 MB
  • pdf0136507638 - (1996) VHDL Made Easy.pdf 13.8 MB
  • pdf0412616505 - (1997) VHDL A logic synthesis approach.pdf 13.4 MB
  • pdf1934404055 - (2007) Digital Circuit Analysis and Design with Simulink Modeling and Introduction to CPLDs and FPGAs 2nd Ed.pdf 13.4 MB
  • pdf0077221435 - (2008) Fundamentals of Digital Logic with VHDL Design - Ed. 3.pdf 12.8 MB
  • pdf0792395980 - (1995) VHDL Coding Styles and Methodologies.pdf 12.7 MB
  • pdf0123744385 - (2009) Low-Power Design of Nanometer FPGAs Architecture and EDA.pdf 12.6 MB
【其他】 Learn VHDL and FPGA Development with a BASYS 3
收录时间:2020-02-05 文档个数:3 文档大小:1.7 GB 最近下载:2024-11-14 人气:2891 磁力链接
  • tgzLearn VHDL and FPGA Development with a BASYS 3.tgz 1.7 GB
  • txtTorrent Downloaded From ExtraTorrent.cc.txt 352 Bytes
  • txtTorrent downloaded from demonoid.pw.txt 46 Bytes
【其他】 Xilinx Vivado Beginners Course to FPGA Development in VHDL
收录时间:2020-02-07 文档个数:3 文档大小:447.2 MB 最近下载:2024-10-04 人气:1138 磁力链接
  • tgzBeginners Course to FPGA Development in VHDL.tgz 447.2 MB
  • txtTorrent Downloaded From ExtraTorrent.cc.txt 352 Bytes
  • txtTorrent downloaded from demonoid.pw.txt 46 Bytes
【其他】 FPGA Design Learning VHDL
收录时间:2020-02-11 文档个数:3 文档大小:1.7 GB 最近下载:2024-11-14 人气:2648 磁力链接
  • tgzFPGA Design Learning VHDL.tgz 1.7 GB
  • txtTorrent Downloaded From ExtraTorrent.cc.txt 352 Bytes
  • txtTorrent downloaded from demonoid.pw.txt 46 Bytes
【影视】 FPGA Development in VHDL - Beyond the Basics
收录时间:2020-02-14 文档个数:91 文档大小:541.2 MB 最近下载:2024-11-06 人气:8224 磁力链接
  • mp403.Working with Custom Data Types/08.Demo.mp4 84.1 MB
  • mp406.Constructing State Machines/05.Demo - Combination Lock (Mealy).mp4 62.8 MB
  • mp405.Keeping Code Organized with Subprograms and Packages/05.Generics.mp4 50.4 MB
  • mp405.Keeping Code Organized with Subprograms and Packages/06.Resolution Functions.mp4 42.9 MB
  • mp406.Constructing State Machines/04.Demo - Traffic Lights (Moore).mp4 41.5 MB
  • mp407.Testing Your Designs/04.Testing with VUnit.mp4 30.8 MB
  • mp402.Developing for the FPGA/05.Demo - Compilation Report.mp4 26.8 MB
  • mp407.Testing Your Designs/03.A Sample Testbench.mp4 26.7 MB
  • mp402.Developing for the FPGA/07.Demo - MATLAB HDL Coder.mp4 23.5 MB
  • mp404.Monitoring Signal States with Attributes/04.Function Kind Attributes.mp4 15.8 MB
  • mp406.Constructing State Machines/06.State Encoding Styles.mp4 13.9 MB
  • mp405.Keeping Code Organized with Subprograms and Packages/03.Procedures.mp4 10.9 MB
  • mp403.Working with Custom Data Types/03.Arrays and Ranges.mp4 10.8 MB
  • mp407.Testing Your Designs/02.Testing and Testbenches.mp4 8.1 MB
  • mp404.Monitoring Signal States with Attributes/03.Value Kind Attributes.mp4 7.5 MB
  • mp403.Working with Custom Data Types/02.Standard Data Types Recap.mp4 6.5 MB
  • mp402.Developing for the FPGA/04.Compilation Process.mp4 5.6 MB
  • mp405.Keeping Code Organized with Subprograms and Packages/04.Constants.mp4 5.0 MB
  • mp404.Monitoring Signal States with Attributes/07.User-defined Attributes.mp4 4.5 MB
  • mp405.Keeping Code Organized with Subprograms and Packages/02.Design Unit Recap.mp4 4.4 MB
【影视】 Getting Started with FPGA Programming with VHDL
收录时间:2020-02-27 文档个数:109 文档大小:520.8 MB 最近下载:2024-11-05 人气:9263 磁力链接
  • mp407.Packages and Components/06.Demo - Packages and Components.mp4 48.3 MB
  • mp408.Debugging and Analysis/02.Simulation with ModelSim.mp4 43.4 MB
  • mp402.FPGA Technology Overview/04.A Look at the Development Board.mp4 39.9 MB
  • mp406.Writing Concurrent Code/07.Demo - Resettable Timer.mp4 39.2 MB
  • mp404.Introduction to VHDL/06.Interacting with Board IO.mp4 31.9 MB
  • mp405.Writing Sequential Code/08.Demo - Sequential Constructs.mp4 31.5 MB
  • mp402.FPGA Technology Overview/05.Setting up the EDA.mp4 20.5 MB
  • mp408.Debugging and Analysis/03.SignalTap Logic Analyzer.mp4 19.8 MB
  • mp402.FPGA Technology Overview/03.What Is an FPGA.mp4 16.9 MB
  • mp404.Introduction to VHDL/04.Ports and Board IO.mp4 15.5 MB
  • mp402.FPGA Technology Overview/06.Project Setup.mp4 13.2 MB
  • mp402.FPGA Technology Overview/08.Programming the FPGA.mp4 10.9 MB
  • mp402.FPGA Technology Overview/07.Pin Assignments and the Pin Planner.mp4 9.8 MB
  • mp401.Course Overview/01.Course Overview.mp4 9.2 MB
  • mp407.Packages and Components/02.The IEEE Library and Standard Logic.mp4 8.0 MB
  • mp403.Digital Design Primer/04.Addition and Multiplication.mp4 8.0 MB
  • mp405.Writing Sequential Code/05.More Data Types.mp4 7.3 MB
  • mp407.Packages and Components/04.Components and Port Maps.mp4 7.3 MB
  • mp403.Digital Design Primer/05.Flip-flop, MUX, and LUT.mp4 7.0 MB
  • mp403.Digital Design Primer/03.Logic Gates.mp4 7.0 MB
【影视】 [udemy] Xilinx Vivado Beginners Course to FPGA Development in VHDL [MyFOM]
收录时间:2020-02-28 文档个数:15 文档大小:483.8 MB 最近下载:2024-11-14 人气:3689 磁力链接
  • mp4Section 2 Lab 1/Implementation of VHDL Design in Vivado and IO Pin Planning.mp4 72.5 MB
  • mp4Section 4 Lab 3/Designing a Microblaze Soft Processor in Vivado IP Integrator.mp4 62.0 MB
  • mp4Section 4 Lab 3/Learn VHDL by Example.mp4 60.0 MB
  • mp4Section 3 Lab 2/Design a Block RAM in IP Integrator.mp4 53.0 MB
  • mp4Section 2 Lab 1/Downloading the Bit-stream to the FPGA.mp4 48.5 MB
  • mp4Section 2 Lab 1/Introduction to the Vivado Design Suite Interface and Creating a New Project.mp4 47.8 MB
  • mp4Section 1 Introduction to Vivado/How to Download and Install Xilinx Vivado Design Suite.mp4 42.2 MB
  • mp4Section 2 Lab 1/Coding and Simulating Simple VHDL in Vivado.mp4 36.2 MB
  • mp4Section 3 Lab 2/Simulating BRAM memory IP in Vivado.mp4 23.3 MB
  • mp4Section 4 Lab 3/Generating a Microblaze using TCL commands in Vivado.mp4 21.1 MB
  • mp4Section 1 Introduction to Vivado/Introduction.mp4 16.9 MB
  • htmlMyFreeOnlineMovies.co.uk.html 189.0 kB
  • txtTorrent Downloaded from Glodls.to.txt 237 Bytes
  • txtSection 4 Lab 3/New Text Document.txt 52 Bytes
  • txtSection 5 Conclusion and Bonus Section/Sorry the files are deleted bare with me.txt 51 Bytes
【文档书籍】 VHDL
收录时间:2020-03-02 文档个数:13 文档大小:99.5 MB 最近下载:2024-11-11 人气:7271 磁力链接
  • pdfEn/[Chu.P.P]_RTL.Hardware.Design.Using.VHDL_(Apr.2006)/[Chu.P.P]_RTL.Hardware.Design.Using.VHDL_(Apr.2006).pdf 35.8 MB
  • djvuRu/[Зотов_В.Ю.]_Проектирование.Встраиваемых.Микропроцессорных.Систем.На.Основе.ПЛИС.Фирмы.XILINX.djvu 26.0 MB
  • pdfRu/[Поляков_А.К.]_Языки.VHDL.и.VERILOG.в.Проектировании.Цифровой.Аппаратуры.pdf 13.8 MB
  • djvuRu/[Бибило_П.Н.]_Основы.Языка.VHDL.djvu 13.0 MB
  • rarEn/[Dueck.R.]_Digital.Design.With.CPLD.Applications.And.VHDL_(2000).rar 7.4 MB
  • rarEn/VHDL.Reference.Manual_(1999).rar 1.4 MB
  • djvuRu/[Сергиенко_А.М.]_VHDL.Для.Проектирования.Вычислительных.Устройств.djvu 1.2 MB
  • rarEn/[Alford.C.]_Digital.Design.VHDL.Laboratory.Notes_(1996).rar 395.4 kB
  • chmRu/[Сергиенко.А.M.]_Изучение.VHDL.chm 320.1 kB
  • rarEn/[Pellerin_D.]_An.Introduction.to.HDLS.for.Simulation.and.Synthesis.rar 147.2 kB
  • chmEn/[Ashenden.P.J.]_The.VHDL.Cookbook_(1990).chm 68.0 kB
  • rarRu/[Каршенбойм.И.]_Шпаргалка.Для.Перехода.От.AHDL.К.VHDL.rar 51.9 kB
  • nfoEn/[Chu.P.P]_RTL.Hardware.Design.Using.VHDL_(Apr.2006)/BBL.nfo 6.8 kB
【文档书籍】 Digital Electronics - A Practical Approach with VHDL - 9th Edition - William Kleitz.pdf
收录时间:2020-03-06 文档个数:1 文档大小:33.6 MB 最近下载:2024-10-27 人气:988 磁力链接
  • pdfDigital Electronics - A Practical Approach with VHDL - 9th Edition - William Kleitz.pdf 33.6 MB
【影视】 [FreeTutorials.Us] Udemy - Learn VHDL and FPGA Development
收录时间:2020-03-06 文档个数:237 文档大小:2.1 GB 最近下载:2024-11-10 人气:2848 磁力链接
  • mp416. Lab 6 - Multiplier/2. BASYS 3 Multiplier Demonstration.mp4 107.3 MB
  • mp45. VHDL Coding Structure/3. VHDL Design Architecture Styles.mp4 102.2 MB
  • mp411. Lab 1 - Full Adder/2. BASYS 3 Full Adder Demonstration.mp4 92.1 MB
  • mp48. FPGA Development Boards/2. BASYS 3 Board Overview.mp4 88.5 MB
  • mp417. Lab 7 - RC Servo/2. BASYS 3 RC Servo Demonstration.mp4 85.6 MB
  • mp44. VHDL Syntax/2. If Statement Case Statement.mp4 79.9 MB
  • mp413. Lab 3 - Universal Shift Register/2. BASYS 3 Universal Shift Register Demonstration.mp4 74.1 MB
  • mp44. VHDL Syntax/3. For Loop While Loop.mp4 73.8 MB
  • mp413. Lab 3 - Universal Shift Register/4. BASYS 2 Universal Shift Register Solution.mp4 73.0 MB
  • mp413. Lab 3 - Universal Shift Register/3. BASYS 2 Universal Shift Register Demonstration.mp4 65.3 MB
  • mp416. Lab 6 - Multiplier/3. BASYS 2 Multiplier Demonstration.mp4 64.9 MB
  • mp45. VHDL Coding Structure/2. VHDL Design Structure.mp4 63.8 MB
  • mp44. VHDL Syntax/6. VHDL Processes and Concurrent Statement.mp4 58.4 MB
  • mp42. Introduction/2. Introduction to VHDL.mp4 58.0 MB
  • mp43. VHDL Data Types/3. Unsigned Signed Data Types.mp4 49.8 MB
  • mp412. Lab 2 - Shift Register/2. BASYS 3 Shift Register Demonstration.mp4 49.1 MB
  • mp46. Test Bench/1. Test Benches Introduction.mp4 48.6 MB
  • mp414. Lab 4 - 7 Segment Display/3. BASYS 2 - 7 Segment Display Demonstration.mp4 47.6 MB
  • mp414. Lab 4 - 7 Segment Display/2. BASYS 3 - 7 Segment Display Demonstration.mp4 46.0 MB
  • mp43. VHDL Data Types/2. Signals Variables Constants.mp4 43.6 MB
【压缩文件】 Vhdl.rar
收录时间:2020-03-20 文档个数:1 文档大小:365.7 MB 最近下载:2024-11-14 人气:1887 磁力链接
  • rarVhdl.rar 365.7 MB
【文档书籍】 VHDL
收录时间:2020-03-24 文档个数:38 文档大小:523.5 MB 最近下载:2024-11-14 人气:1955 磁力链接
  • pdf0792384741 {DFB0D3D0} VHDL_ Coding Styles and Methodologies_ An In-Depth Tutorial (2nd ed.) [Cohen 1999-03-31].pdf 51.1 MB
  • pdf0471720925 {C124FE1E} RTL Hardware Design using VHDL_ Coding for Efficiency, Portability, and Scalability [Chu 2006-04-14].pdf 35.8 MB
  • pdf0072460857 {E22DB062} Fundamentals of Digital Logic with VHDL Design (2nd ed.) [Brown & Vranesic 2005].pdf 35.6 MB
  • pdf1401840302 {7F60FA41} Digital Design with CPLD Applications and VHDL (2nd ed.) [Dueck 2011-09-09].pdf 35.3 MB
  • pdf0072460857 {D7B1B43E} Fundamentals of Digital Logic with VHDL Design (2nd ed.) [Brown & Vranesic 2005].pdf 34.2 MB
  • pdf0132543036 {3E1F9F14} Digital Electronics_ A Practical Approach with VHDL (9th ed.) [Kleitz 2011-07-28].pdf 33.6 MB
  • pdf0132543036 {2ABEC942} Digital Electronics_ A Practical Approach with VHDL (9th ed.) [Kleitz 2011-07-28].pdf 33.6 MB
  • pdf0072460857 {1DC21D23} Fundamentals of Digital Logic with VHDL Design (2nd ed.) [Brown & Vranesic 2005].pdf 31.9 MB
  • pdf1420061313 {B15B8D48} Digital Design_ Basic Concepts and Principles (VHDL) [Karim & Chen 2007-11-27].pdf 24.2 MB
  • pdf0470185317 {8B57CD6C} FPGA Prototyping by VHDL Examples_ Xilinx Spartan-3 Version [Chu 2008-02-04].pdf 22.3 MB
  • pdf0132543036 {EA4CF456} Digital Electronics_ A Practical Approach with VHDL (9th ed.) [Kleitz 2011-07-28].pdf 21.5 MB
  • pdf0136507638 {14BF29BF} VHDL Made Easy! [Pellerin & Taylor 1996-09-03].pdf 13.8 MB
  • pdf0073529532 {6B2C9147} Fundamentals of Digital Logic with VHDL Design (3rd ed.) [Brown & Vranesic 2008-04-14].pdf 12.8 MB
  • pdf0792395980 {FF6C4B10} VHDL_ Coding Styles and Methodologies [Cohen 1995-08-31] (bad scan).pdf 12.7 MB
  • pdf0262014335, 8120343018 {8654483B} Circuit Design and Simulation with VHDL (2nd ed.) [Pedroni 2010-09-17].pdf 10.8 MB
  • pdf0073380695 {EA6DB88C} Fundamentals of Digital and Computer Design with VHDL [Sandige & Sandige 2011-09-23].pdf 9.6 MB
  • pdf0766811603 {AC6D1BFF} Digital Design with CPLD Applications and VHDL [Dueck 2000-06-28].pdf 9.0 MB
  • pdf0766811603 {584B230D} Digital Design with CPLD Applications and VHDL [Dueck 2000-06-28].pdf 9.0 MB
  • pdf3319025465 {1A2E0638} Synthesizable VHDL Design for FPGAs [Bezerra & Lettnin 2013-10-31].pdf 8.2 MB
  • pdf0769500234 {F937C62E} Digital Systems Design with VHDL and Synthesis_ An Integrated Approach [Chang 1999-05-11].pdf 7.3 MB
【压缩文件】 [ FreeCourseWeb.com ] Udemy - Xilinx FPGAs- Learning Through Labs using VHDL.zip
收录时间:2020-03-30 文档个数:1 文档大小:1.2 GB 最近下载:2024-10-02 人气:1596 磁力链接
  • zip[ FreeCourseWeb.com ] Udemy - Xilinx FPGAs- Learning Through Labs using VHDL.zip 1.2 GB
【影视】 [FreeTutorials.Us] Udemy - Learn VHDL and FPGA Development
收录时间:2020-03-30 文档个数:237 文档大小:2.1 GB 最近下载:2020-03-30 人气:2 磁力链接
  • mp416. Lab 6 - Multiplier/2. BASYS 3 Multiplier Demonstration.mp4 107.3 MB
  • mp45. VHDL Coding Structure/3. VHDL Design Architecture Styles.mp4 102.2 MB
  • mp411. Lab 1 - Full Adder/2. BASYS 3 Full Adder Demonstration.mp4 92.1 MB
  • mp48. FPGA Development Boards/2. BASYS 3 Board Overview.mp4 88.5 MB
  • mp417. Lab 7 - RC Servo/2. BASYS 3 RC Servo Demonstration.mp4 85.6 MB
  • mp44. VHDL Syntax/2. If Statement Case Statement.mp4 79.9 MB
  • mp413. Lab 3 - Universal Shift Register/2. BASYS 3 Universal Shift Register Demonstration.mp4 74.1 MB
  • mp44. VHDL Syntax/3. For Loop While Loop.mp4 73.8 MB
  • mp413. Lab 3 - Universal Shift Register/4. BASYS 2 Universal Shift Register Solution.mp4 73.0 MB
  • mp413. Lab 3 - Universal Shift Register/3. BASYS 2 Universal Shift Register Demonstration.mp4 65.3 MB
  • mp416. Lab 6 - Multiplier/3. BASYS 2 Multiplier Demonstration.mp4 64.9 MB
  • mp45. VHDL Coding Structure/2. VHDL Design Structure.mp4 63.8 MB
  • mp44. VHDL Syntax/6. VHDL Processes and Concurrent Statement.mp4 58.4 MB
  • mp42. Introduction/2. Introduction to VHDL.mp4 58.0 MB
  • mp43. VHDL Data Types/3. Unsigned Signed Data Types.mp4 49.8 MB
  • mp412. Lab 2 - Shift Register/2. BASYS 3 Shift Register Demonstration.mp4 49.1 MB
  • mp46. Test Bench/1. Test Benches Introduction.mp4 48.6 MB
  • mp414. Lab 4 - 7 Segment Display/3. BASYS 2 - 7 Segment Display Demonstration.mp4 47.6 MB
  • mp414. Lab 4 - 7 Segment Display/2. BASYS 3 - 7 Segment Display Demonstration.mp4 46.0 MB
  • mp43. VHDL Data Types/2. Signals Variables Constants.mp4 43.6 MB
【其他】 vhdl software
收录时间:2020-04-07 文档个数:589 文档大小:3.1 GB 最近下载:2024-11-07 人气:143 磁力链接
  • xzidata/drop223.zip.xz 151.8 MB
  • xzidata/drop221.zip.xz 141.0 MB
  • xzidata/drop224.zip.xz 124.5 MB
  • xzidata/drop222.zip.xz 115.2 MB
  • xzidata/drop328.zip.xz 112.0 MB
  • xzidata/drop108.zip.xz 89.6 MB
  • xzidata/drop225.zip.xz 86.4 MB
  • xzidata/drop162.zip.xz 70.3 MB
  • xzidata/drop361.zip.xz 67.7 MB
  • xzidata/drop19.zip.xz 67.0 MB
  • xzidata/drop354.zip.xz 64.3 MB
  • xzidata/drop229.zip.xz 63.7 MB
  • xzidata/drop174.zip.xz 60.5 MB
  • xzidata/drop302.zip.xz 59.3 MB
  • xzidata/drop143.zip.xz 59.1 MB
  • xzidata/drop306.zip.xz 53.5 MB
  • xzidata/drop60.zip.xz 49.9 MB
  • xzidata/drop75.zip.xz 47.1 MB
  • xzidata/drop61.zip.xz 47.0 MB
  • xzidata/drop273.zip.xz 47.0 MB
【压缩文件】 XILINX 3.1 & Active VHDL.rar
收录时间:2020-04-10 文档个数:1 文档大小:503.1 MB 最近下载:2023-02-05 人气:80 磁力链接
  • rarXILINX 3.1 & Active VHDL.rar 503.1 MB
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