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序列：- 【影视】 [ DevCourseWeb.com ] Udemy - Simple Axi Bus Design Using Verilog Hdl
- 收录时间:2024-01-29 文档个数:27 文档大小:624.1 MB 最近下载:2024-10-08 人气:352 磁力链接
~Get Your Files Here !/4 - Source code/14 - Design of AXI bus using verilog HDL write process.mp4 292.9 MB- ~Get Your Files Here !/4 - Source code/15 - Design of AXI bus using verilog HDL Read process.mp4 129.3 MB
- ~Get Your Files Here !/1 - Course Introduction/1 - Introduction.mp4 23.6 MB
- ~Get Your Files Here !/2 - AXI bus/8 - Signal Diagram.mp4 20.9 MB
- ~Get Your Files Here !/4 - Source code/17 - Test bench simulation.mp4 19.9 MB
- ~Get Your Files Here !/2 - AXI bus/5 - AXI channel Architecture of Readwrites.mp4 18.4 MB
- ~Get Your Files Here !/2 - AXI bus/10 - Read process Timing diagram.mp4 15.8 MB
- ~Get Your Files Here !/1 - Course Introduction/3 - Comparision between AHB AXI APB.mp4 13.5 MB
- ~Get Your Files Here !/4 - Source code/16 - AXI master slave.mp4 13.4 MB
- ~Get Your Files Here !/2 - AXI bus/9 - Write process Timing diagram.mp4 12.7 MB
- ~Get Your Files Here !/2 - AXI bus/6 - AXI signals.mp4 12.6 MB
- ~Get Your Files Here !/2 - AXI bus/7 - Handshaking signals.mp4 12.5 MB
- ~Get Your Files Here !/3 - Implementation of Simple AXI bus/13 - AXI MasterSlave Block diagram and Writeread process.mp4 11.6 MB
- ~Get Your Files Here !/2 - AXI bus/11 - Dependencies between channel handshake signals.mp4 11.5 MB
- ~Get Your Files Here !/1 - Course Introduction/2 - AMBA introduction.mp4 6.6 MB
- ~Get Your Files Here !/2 - AXI bus/4 - Introduction to AXI.mp4 6.4 MB
- ~Get Your Files Here !/3 - Implementation of Simple AXI bus/12 - AXI state machine for write read.mp4 2.5 MB
~Get Your Files Here !/4 - Source code/14 - axi-master-write.v 3.2 kB- ~Get Your Files Here !/4 - Source code/14 - axi-slave-write.v 2.7 kB
- ~Get Your Files Here !/4 - Source code/15 - axi-master-read.v 2.6 kB
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- 【影视】 [ DevCourseWeb.com ] Udemy - Building Custom AXI Interface Peripherals for ZYNQ Devices
- 收录时间:2022-05-04 文档个数:131 文档大小:3.2 GB 最近下载:2024-09-29 人气:2783 磁力链接
- ~Get Your Files Here !/7 - Adding Interrupts with Vivado Template/37 - Using Vivado Interrupt Template Code P2.mp4 224.0 MB
- ~Get Your Files Here !/8 - Adding Master Interface/45 - Creating Master Interface with Vivado Template P1.mp4 170.4 MB
- ~Get Your Files Here !/7 - Adding Interrupts with Vivado Template/42 - Blinking Effect with Interrupt.mp4 158.1 MB
- ~Get Your Files Here !/6 - Adding Interrupts to Slave Lite Interfaces/33 - Adding Interrupt with RTL P2.mp4 156.5 MB
- ~Get Your Files Here !/10 - AXI Stream Master Interface with Vivado Template/55 - Creating AXIS Master Interface P1.mp4 152.3 MB
- ~Get Your Files Here !/9 - AXI Stream Slave Interface with Vivado Template/49 - Building AXIS Slave Interface P1.mp4 145.6 MB
- ~Get Your Files Here !/7 - Adding Interrupts with Vivado Template/36 - Using Vivado Interrupt Template Code P1.mp4 104.9 MB
- ~Get Your Files Here !/4 - Understanding AXI4-Lite Signals/23 - Analyzing Signals on ILA Probe.mp4 102.9 MB
- ~Get Your Files Here !/5 - Adding AXI Lite Interface for existing Verilog Code/25 - Add Existing RTL Delay Generator P1.mp4 98.3 MB
- ~Get Your Files Here !/6 - Adding Interrupts to Slave Lite Interfaces/32 - Adding Interrupt with RTL P1.mp4 94.8 MB
- ~Get Your Files Here !/4 - Understanding AXI4-Lite Signals/21 - Other Signals in Slave Lite Interface.mp4 93.9 MB
- ~Get Your Files Here !/5 - Adding AXI Lite Interface for existing Verilog Code/27 - Adding Existing RTL Multiplier P1.mp4 87.1 MB
- ~Get Your Files Here !/6 - Adding Interrupts to Slave Lite Interfaces/31 - Fundamentals of Interrupt C Application.mp4 84.5 MB
- ~Get Your Files Here !/2 - Building AXI Slave Lite Interface Using Vivado Template without I O ports/7 - Slave Lite Interface without I O Ports P4 Creating C Application.mp4 80.0 MB
- ~Get Your Files Here !/9 - AXI Stream Slave Interface with Vivado Template/50 - Building AXIS Slave Interface P2.mp4 68.7 MB
- ~Get Your Files Here !/9 - AXI Stream Slave Interface with Vivado Template/52 - Building Complex FSM with existing FSM for AXIS.mp4 67.1 MB
- ~Get Your Files Here !/8 - Adding Master Interface/46 - Creating Master Interface with Vivado Template P2.mp4 65.7 MB
- ~Get Your Files Here !/11 - AXIS Slave Interface with Verilog/60 - Building AXIS Slave Interface with Verilog P2.mp4 64.6 MB
- ~Get Your Files Here !/12 - AXIS Master Slave Interface with Verilog/64 - Building AXIS Master Slave Interface with Verilog P1.mp4 60.3 MB
- ~Get Your Files Here !/7 - Adding Interrupts with Vivado Template/39 - Modifying Delay of the Vivado Interrupt Template.mp4 58.0 MB
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