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【影视】 FPGA Development in VHDL - Beyond the Basics

收录时间:2020-02-14 文档个数:91 文档大小:541.2 MB 最近下载:2024-11-06 人气:8224 磁力链接

03.Working with Custom Data Types/08.Demo.mp4 84.1 MB
06.Constructing State Machines/05.Demo - Combination Lock (Mealy).mp4 62.8 MB
05.Keeping Code Organized with Subprograms and Packages/05.Generics.mp4 50.4 MB
05.Keeping Code Organized with Subprograms and Packages/06.Resolution Functions.mp4 42.9 MB
06.Constructing State Machines/04.Demo - Traffic Lights (Moore).mp4 41.5 MB
07.Testing Your Designs/04.Testing with VUnit.mp4 30.8 MB
02.Developing for the FPGA/05.Demo - Compilation Report.mp4 26.8 MB
07.Testing Your Designs/03.A Sample Testbench.mp4 26.7 MB
02.Developing for the FPGA/07.Demo - MATLAB HDL Coder.mp4 23.5 MB
04.Monitoring Signal States with Attributes/04.Function Kind Attributes.mp4 15.8 MB
06.Constructing State Machines/06.State Encoding Styles.mp4 13.9 MB
05.Keeping Code Organized with Subprograms and Packages/03.Procedures.mp4 10.9 MB
03.Working with Custom Data Types/03.Arrays and Ranges.mp4 10.8 MB
07.Testing Your Designs/02.Testing and Testbenches.mp4 8.1 MB
04.Monitoring Signal States with Attributes/03.Value Kind Attributes.mp4 7.5 MB
03.Working with Custom Data Types/02.Standard Data Types Recap.mp4 6.5 MB
02.Developing for the FPGA/04.Compilation Process.mp4 5.6 MB
05.Keeping Code Organized with Subprograms and Packages/04.Constants.mp4 5.0 MB
04.Monitoring Signal States with Attributes/07.User-defined Attributes.mp4 4.5 MB
05.Keeping Code Organized with Subprograms and Packages/02.Design Unit Recap.mp4 4.4 MB

猜你喜欢： Development Basics Beyond VHDL FPGA

【影视】 Getting Started with FPGA Programming with VHDL

收录时间:2020-02-27 文档个数:109 文档大小:520.8 MB 最近下载:2024-11-05 人气:9263 磁力链接

07.Packages and Components/06.Demo - Packages and Components.mp4 48.3 MB
08.Debugging and Analysis/02.Simulation with ModelSim.mp4 43.4 MB
02.FPGA Technology Overview/04.A Look at the Development Board.mp4 39.9 MB
06.Writing Concurrent Code/07.Demo - Resettable Timer.mp4 39.2 MB
04.Introduction to VHDL/06.Interacting with Board IO.mp4 31.9 MB
05.Writing Sequential Code/08.Demo - Sequential Constructs.mp4 31.5 MB
02.FPGA Technology Overview/05.Setting up the EDA.mp4 20.5 MB
08.Debugging and Analysis/03.SignalTap Logic Analyzer.mp4 19.8 MB
02.FPGA Technology Overview/03.What Is an FPGA.mp4 16.9 MB
04.Introduction to VHDL/04.Ports and Board IO.mp4 15.5 MB
02.FPGA Technology Overview/06.Project Setup.mp4 13.2 MB
02.FPGA Technology Overview/08.Programming the FPGA.mp4 10.9 MB
02.FPGA Technology Overview/07.Pin Assignments and the Pin Planner.mp4 9.8 MB
01.Course Overview/01.Course Overview.mp4 9.2 MB
07.Packages and Components/02.The IEEE Library and Standard Logic.mp4 8.0 MB
03.Digital Design Primer/04.Addition and Multiplication.mp4 8.0 MB
05.Writing Sequential Code/05.More Data Types.mp4 7.3 MB
07.Packages and Components/04.Components and Port Maps.mp4 7.3 MB
03.Digital Design Primer/05.Flip-flop, MUX, and LUT.mp4 7.0 MB
03.Digital Design Primer/03.Logic Gates.mp4 7.0 MB

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【影视】 [udemy] Xilinx Vivado Beginners Course to FPGA Development in VHDL [MyFOM]

收录时间:2020-02-28 文档个数:15 文档大小:483.8 MB 最近下载:2024-11-14 人气:3689 磁力链接

Section 2 Lab 1/Implementation of VHDL Design in Vivado and IO Pin Planning.mp4 72.5 MB
Section 4 Lab 3/Designing a Microblaze Soft Processor in Vivado IP Integrator.mp4 62.0 MB
Section 4 Lab 3/Learn VHDL by Example.mp4 60.0 MB
Section 3 Lab 2/Design a Block RAM in IP Integrator.mp4 53.0 MB
Section 2 Lab 1/Downloading the Bit-stream to the FPGA.mp4 48.5 MB
Section 2 Lab 1/Introduction to the Vivado Design Suite Interface and Creating a New Project.mp4 47.8 MB
Section 1 Introduction to Vivado/How to Download and Install Xilinx Vivado Design Suite.mp4 42.2 MB
Section 2 Lab 1/Coding and Simulating Simple VHDL in Vivado.mp4 36.2 MB
Section 3 Lab 2/Simulating BRAM memory IP in Vivado.mp4 23.3 MB
Section 4 Lab 3/Generating a Microblaze using TCL commands in Vivado.mp4 21.1 MB
Section 1 Introduction to Vivado/Introduction.mp4 16.9 MB
MyFreeOnlineMovies.co.uk.html 189.0 kB
Torrent Downloaded from Glodls.to.txt 237 Bytes
Section 4 Lab 3/New Text Document.txt 52 Bytes
Section 5 Conclusion and Bonus Section/Sorry the files are deleted bare with me.txt 51 Bytes

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【影视】 [FreeTutorials.Us] Udemy - Learn VHDL and FPGA Development

收录时间:2020-03-06 文档个数:237 文档大小:2.1 GB 最近下载:2024-11-10 人气:2848 磁力链接

16. Lab 6 - Multiplier/2. BASYS 3 Multiplier Demonstration.mp4 107.3 MB
5. VHDL Coding Structure/3. VHDL Design Architecture Styles.mp4 102.2 MB
11. Lab 1 - Full Adder/2. BASYS 3 Full Adder Demonstration.mp4 92.1 MB
8. FPGA Development Boards/2. BASYS 3 Board Overview.mp4 88.5 MB
17. Lab 7 - RC Servo/2. BASYS 3 RC Servo Demonstration.mp4 85.6 MB
4. VHDL Syntax/2. If Statement Case Statement.mp4 79.9 MB
13. Lab 3 - Universal Shift Register/2. BASYS 3 Universal Shift Register Demonstration.mp4 74.1 MB
4. VHDL Syntax/3. For Loop While Loop.mp4 73.8 MB
13. Lab 3 - Universal Shift Register/4. BASYS 2 Universal Shift Register Solution.mp4 73.0 MB
13. Lab 3 - Universal Shift Register/3. BASYS 2 Universal Shift Register Demonstration.mp4 65.3 MB
16. Lab 6 - Multiplier/3. BASYS 2 Multiplier Demonstration.mp4 64.9 MB
5. VHDL Coding Structure/2. VHDL Design Structure.mp4 63.8 MB
4. VHDL Syntax/6. VHDL Processes and Concurrent Statement.mp4 58.4 MB
2. Introduction/2. Introduction to VHDL.mp4 58.0 MB
3. VHDL Data Types/3. Unsigned Signed Data Types.mp4 49.8 MB
12. Lab 2 - Shift Register/2. BASYS 3 Shift Register Demonstration.mp4 49.1 MB
6. Test Bench/1. Test Benches Introduction.mp4 48.6 MB
14. Lab 4 - 7 Segment Display/3. BASYS 2 - 7 Segment Display Demonstration.mp4 47.6 MB
14. Lab 4 - 7 Segment Display/2. BASYS 3 - 7 Segment Display Demonstration.mp4 46.0 MB
3. VHDL Data Types/2. Signals Variables Constants.mp4 43.6 MB

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【影视】 [FreeTutorials.Us] Udemy - Learn VHDL and FPGA Development

收录时间:2020-03-30 文档个数:237 文档大小:2.1 GB 最近下载:2020-03-30 人气:2 磁力链接

16. Lab 6 - Multiplier/2. BASYS 3 Multiplier Demonstration.mp4 107.3 MB
5. VHDL Coding Structure/3. VHDL Design Architecture Styles.mp4 102.2 MB
11. Lab 1 - Full Adder/2. BASYS 3 Full Adder Demonstration.mp4 92.1 MB
8. FPGA Development Boards/2. BASYS 3 Board Overview.mp4 88.5 MB
17. Lab 7 - RC Servo/2. BASYS 3 RC Servo Demonstration.mp4 85.6 MB
4. VHDL Syntax/2. If Statement Case Statement.mp4 79.9 MB
13. Lab 3 - Universal Shift Register/2. BASYS 3 Universal Shift Register Demonstration.mp4 74.1 MB
4. VHDL Syntax/3. For Loop While Loop.mp4 73.8 MB
13. Lab 3 - Universal Shift Register/4. BASYS 2 Universal Shift Register Solution.mp4 73.0 MB
13. Lab 3 - Universal Shift Register/3. BASYS 2 Universal Shift Register Demonstration.mp4 65.3 MB
16. Lab 6 - Multiplier/3. BASYS 2 Multiplier Demonstration.mp4 64.9 MB
5. VHDL Coding Structure/2. VHDL Design Structure.mp4 63.8 MB
4. VHDL Syntax/6. VHDL Processes and Concurrent Statement.mp4 58.4 MB
2. Introduction/2. Introduction to VHDL.mp4 58.0 MB
3. VHDL Data Types/3. Unsigned Signed Data Types.mp4 49.8 MB
12. Lab 2 - Shift Register/2. BASYS 3 Shift Register Demonstration.mp4 49.1 MB
6. Test Bench/1. Test Benches Introduction.mp4 48.6 MB
14. Lab 4 - 7 Segment Display/3. BASYS 2 - 7 Segment Display Demonstration.mp4 47.6 MB
14. Lab 4 - 7 Segment Display/2. BASYS 3 - 7 Segment Display Demonstration.mp4 46.0 MB
3. VHDL Data Types/2. Signals Variables Constants.mp4 43.6 MB

猜你喜欢： Development VHDL FPGA FreeTutorials Us Udemy Learn

【影视】 Get Started with VHDL Programming Design Your Own Hardware

收录时间:2020-12-26 文档个数:90 文档大小:1.1 GB 最近下载:2024-11-15 人气:4420 磁力链接

[TutsNode.com] - Get Started with VHDL Programming Design Your Own Hardware/6. VHDL Program Structure/1. VHDL Program Structure.mp4 119.0 MB
[TutsNode.com] - Get Started with VHDL Programming Design Your Own Hardware/13. Difference between Signals and Variables in VHDL/1. Difference between Signals and Variables in VHDL.mp4 112.3 MB
[TutsNode.com] - Get Started with VHDL Programming Design Your Own Hardware/14. Wait on and Wait Until in VHDL/1. Wait on and Wait Until in VHDL.mp4 81.4 MB
[TutsNode.com] - Get Started with VHDL Programming Design Your Own Hardware/15. Conditional Statements In VHDL IF THEN ELSIF ELSE/1. Conditional Statements In VHDL IF THEN ELSIF ELSE.mp4 64.2 MB
[TutsNode.com] - Get Started with VHDL Programming Design Your Own Hardware/7. Extra/1. Download and Install.mp4 58.0 MB
[TutsNode.com] - Get Started with VHDL Programming Design Your Own Hardware/16. Sensitivity List in VHDL/1. Create a Process with A Sensitivity List in VHDL.mp4 57.9 MB
[TutsNode.com] - Get Started with VHDL Programming Design Your Own Hardware/17. Std_logic Datatype/1. Std_logic Datatype.mp4 54.7 MB
[TutsNode.com] - Get Started with VHDL Programming Design Your Own Hardware/13. Difference between Signals and Variables in VHDL/2. Test the Difference between Signals and Variables in VHDL.mp4 53.9 MB
[TutsNode.com] - Get Started with VHDL Programming Design Your Own Hardware/15. Conditional Statements In VHDL IF THEN ELSIF ELSE/2. Test Conditional Statements In VHDL.mp4 39.6 MB
[TutsNode.com] - Get Started with VHDL Programming Design Your Own Hardware/8. Write Your First VHDL Code/1. Write Your First VHDL Code.mp4 37.9 MB
[TutsNode.com] - Get Started with VHDL Programming Design Your Own Hardware/17. Std_logic Datatype/2. Simple Test Std_logic DataType.mp4 37.8 MB
[TutsNode.com] - Get Started with VHDL Programming Design Your Own Hardware/5. VHDL Design Flow/1. VHDL Design Flow.mp4 36.8 MB
[TutsNode.com] - Get Started with VHDL Programming Design Your Own Hardware/14. Wait on and Wait Until in VHDL/2. Test Wait on and Wait Until in VHDL.mp4 33.9 MB
[TutsNode.com] - Get Started with VHDL Programming Design Your Own Hardware/10. Loop and Exit in VHDL/1. How to use Loop and Exit in VHDL.mp4 32.3 MB
[TutsNode.com] - Get Started with VHDL Programming Design Your Own Hardware/8. Write Your First VHDL Code/2. Test Hello World Code.mp4 31.4 MB
[TutsNode.com] - Get Started with VHDL Programming Design Your Own Hardware/12. While Loop in VHDL/2. Test While Loop in VHDL.mp4 27.1 MB
[TutsNode.com] - Get Started with VHDL Programming Design Your Own Hardware/2. VHDL/1. What is VHDL.mp4 24.4 MB
[TutsNode.com] - Get Started with VHDL Programming Design Your Own Hardware/16. Sensitivity List in VHDL/2. Test Sensitivity List in VHDL.mp4 23.3 MB
[TutsNode.com] - Get Started with VHDL Programming Design Your Own Hardware/11. For-Loop in VHDL/1. How to use For-Loop in VHDL.mp4 21.9 MB
[TutsNode.com] - Get Started with VHDL Programming Design Your Own Hardware/9. Time delay in VHDL/1. How to add a time delay in VHDL.mp4 20.6 MB

猜你喜欢： Own VHDL Get Started Programming Hardware Design Your

【影视】 [ CourseBoat.com ] Udemy - Designing Digital Systems Using VHDL - An introduction

收录时间:2021-10-22 文档个数:246 文档大小:3.5 GB 最近下载:2024-11-15 人气:4333 磁力链接

~Get Your Files Here !/4. Start of simulation and design/11. Changing the names of the signals.mp4 136.8 MB
~Get Your Files Here !/4. Start of simulation and design/18. Seneric inside NTT.mp4 130.1 MB
~Get Your Files Here !/4. Start of simulation and design/9. Test Bench Types.mp4 117.3 MB
~Get Your Files Here !/4. Start of simulation and design/16. Demultiplexter.mp4 101.4 MB
~Get Your Files Here !/4. Start of simulation and design/27. Type Conversion Simulation.mp4 97.4 MB
~Get Your Files Here !/4. Start of simulation and design/21. Generic Example.mp4 75.1 MB
~Get Your Files Here !/4. Start of simulation and design/22. ISE Library Section.mp4 73.5 MB
~Get Your Files Here !/2. basic concepts of digital/7. Sequential logic idea.mp4 71.7 MB
~Get Your Files Here !/4. Start of simulation and design/7. Designing the Gate Level.mp4 70.1 MB
~Get Your Files Here !/4. Start of simulation and design/14. BCD code to Excess-3.mp4 61.2 MB
~Get Your Files Here !/3. tips to use ISE/16. ISE warnings.mp4 57.3 MB
~Get Your Files Here !/4. Start of simulation and design/26. Type Conversion in ISE.mp4 51.5 MB
~Get Your Files Here !/2. basic concepts of digital/52. Synchronous vs Asynchronous.mp4 50.8 MB
~Get Your Files Here !/3. tips to use ISE/14. ISE Schematic.mp4 48.8 MB
~Get Your Files Here !/3. tips to use ISE/8. FIFO operation.mp4 47.6 MB
~Get Your Files Here !/3. tips to use ISE/13. Synthesize.mp4 46.5 MB
~Get Your Files Here !/3. tips to use ISE/15. ISE Signals.mp4 46.3 MB
~Get Your Files Here !/3. tips to use ISE/12. ISE Design properties.mp4 46.1 MB
~Get Your Files Here !/2. basic concepts of digital/2. Basic Concepts of Digital.mp4 45.0 MB
~Get Your Files Here !/3. tips to use ISE/9. General Purpose processor.mp4 41.1 MB

猜你喜欢： VHDL introduction Designing Udemy CourseBoat Systems Digital Using com

【影视】 [ TutPig.com ] Udemy - Learn VHDL, PLS's and FPGA (Digital Electronic 2)

收录时间:2021-12-08 文档个数:53 文档大小:3.2 GB 最近下载:2024-10-23 人气:2111 磁力链接

~Get Your Files Here !/12. Processor Design and its VHDL/1. Simple Processor Design and its VHDL.mp4 489.0 MB
~Get Your Files Here !/5. Multiplexers and Shannon Expansion/1. Multiplexers and Shannon Expansion.mp4 323.1 MB
~Get Your Files Here !/4. VHDL Adders Multiplier Narrated/1. VHDL for adders, Multiplier.mp4 308.1 MB
~Get Your Files Here !/11. VHDL code of the bus design with SWAP operation/1. VHDL code of the bus design with SWAP operation.mp4 238.9 MB
~Get Your Files Here !/3. Half Adders, Full Adders, RCA, CLA/1. HA FA RCA CLA.mp4 209.8 MB
~Get Your Files Here !/7. Conditional statement generate statement/1. Conditional statement, Generate statement, Sequential Assignment, VHDL operators.mp4 205.8 MB
~Get Your Files Here !/6. Decoders Arithmetic Comparator Selected signal assignment/1. Decoders, Arithmetic Comparator, Selected signal assignment.mp4 199.4 MB
~Get Your Files Here !/13. Modelsim/3. Modelsim Tutorial 2.mp4 198.7 MB
~Get Your Files Here !/9. VHDL gated latches flipflops, registers and counter/1. VHDL for Latches, FlipFlops, registers and counters.mp4 166.1 MB
~Get Your Files Here !/10. VHDL parallel load counters and bus design/1. Parallel Load counters and bus design.mp4 163.5 MB
~Get Your Files Here !/1. Introduction/1. Introduction to CAD tools.mp4 152.4 MB
~Get Your Files Here !/13. Modelsim/2. Modelsim Tutorial 1.mp4 134.6 MB
~Get Your Files Here !/8. latches flipflops shift and parallel access registers/1. Latches, FlipFlops, parallel access and shift registers.mp4 122.1 MB
~Get Your Files Here !/2. Numbers Representations & LUTs, PLDs, FPGA/2. LUTs, PLDs, FPGA.mp4 116.6 MB
~Get Your Files Here !/2. Numbers Representations & LUTs, PLDs, FPGA/1. Numbers Representations.mp4 93.2 MB
~Get Your Files Here !/1. Introduction/1.1 Fundamentals Of Digital Logic With VHDL Design 3rd Edition.pdf 12.8 MB
~Get Your Files Here !/4. VHDL Adders Multiplier Narrated/1.1 CENG335 Lecture 2 VHDL Adders Multiplier Narrated.pptx 3.4 MB
~Get Your Files Here !/3. Half Adders, Full Adders, RCA, CLA/1.1 CENG335 Lecture 3 HA FA RCA CLA.pptx 3.0 MB
~Get Your Files Here !/5. Multiplexers and Shannon Expansion/1.1 CENG335 Lecture 4 Multiplexers and Shannon Expansion.pptx 2.6 MB
~Get Your Files Here !/12. Processor Design and its VHDL/1.6 Exercises_set1_solution_part2.pdf 2.5 MB

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【影视】 VHDL Circuit Design and FPGAs with VIVADO and MODELSIM

收录时间:2022-11-24 文档个数:171 文档大小:10.5 GB 最近下载:2024-09-16 人气:187 磁力链接

03 - Combinational Circuit Design in VHDL/003 VIVADO Application_ Generate Statement, MUX 2x1 and When-Else statement.mp4 517.6 MB
02 - Entity, Architecture and VHDL Operators/008 VIVADO Application_ Shift operators and abs() function simulation in VIVADO.mp4 515.7 MB
03 - Combinational Circuit Design in VHDL/006 VIVADO Application_ IO Planning Using Vivado.mp4 492.8 MB
07 - Sequential circuits, process, clock divider, sample seq. circ. implementations/006 VIVADO Application_ Parallel Operation, Signal Objects vs Variable Objects.mp4 450.9 MB
02 - Entity, Architecture and VHDL Operators/006 VIVADO Application_ Negative Numbers in VHDL, Positive and Natural Numbers.mp4 378.9 MB
02 - Entity, Architecture and VHDL Operators/011 VIVADO Application_ Power operator __, rem() and mod() simulation in VIVADO.mp4 365.3 MB
04 - Simulation of VHDL Programs, and Testbench Writing/003 VIVADO Application_ Writing TEST-BENCH and VIVADO Simulation Using TEST-BENCH.mp4 355.3 MB
13 - Fixed and Floating Point Numbers in VHDL/001 Simulation of Fixed-Point VHDL Implementations in VIVADO.mp4 354.5 MB
02 - Entity, Architecture and VHDL Operators/004 VIVADO Application_ Creating I_O Ports for Different Data Types and Port Pin Num.mp4 354.4 MB
11 - Intellectual Property (IP) Cores, and Use of IP Cores for VHDL Design/001 VIVADO Application_ Add_Subtract IP Code use in VHDL Code.mp4 333.7 MB
06 - User Defined Data Types, Constrained and Unconstrained Arrays, Matrices in VHDL/003 Matrices and 3D arrays in VHDL.mp4 276.4 MB
12 - Programming FPGA Using ARTY-7 35T Evaluation Board and VIvado/001 Constraints Files Used For the Programming of FPGAs.mp4 272.0 MB
07 - Sequential circuits, process, clock divider, sample seq. circ. implementations/011 MODELSIM Simulation_ Clock Division in VHDL, Part-1.mp4 261.0 MB
07 - Sequential circuits, process, clock divider, sample seq. circ. implementations/009 MODELSIM Simulation_ Signal Object Behavior-2.mp4 251.5 MB
10 - Packages, Components, Functions, Procedures/004 VIVADO Application_ Defining components and using them in VHDL codes.mp4 246.3 MB
12 - Programming FPGA Using ARTY-7 35T Evaluation Board and VIvado/002 Programming FPGA Using ARTY-7 35T Evaluation Board and XILINX VIVADO.mp4 240.4 MB
03 - Combinational Circuit Design in VHDL/008 Binary Encoders in VHDL.mp4 223.3 MB
06 - User Defined Data Types, Constrained and Unconstrained Arrays, Matrices in VHDL/004 MODELSIM Simulation for user-defined data type attributes.mp4 208.7 MB
09 - Loops in VHDL/001 Loops in VHDL.mp4 178.0 MB
04 - Simulation of VHDL Programs, and Testbench Writing/001 Testbench writing for the simulation of VHDL programs.mp4 175.3 MB

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【影视】 [ DevCourseWeb.com ] Introduction To Vhdl - Udemy

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[ DevCourseWeb.com ] Introduction To Vhdl - Udemy 643.9 MB

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【影视】 [ DevCourseWeb.com ] Udemy - Xilinx Fpgas - Learning Through Labs Using Vhdl

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[ DevCourseWeb.com ] Udemy - Xilinx Fpgas - Learning Through Labs Using Vhdl 1.3 GB

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